Design of a 25nm Physical Gate Length Bulk-PMOS in Silicon 4/10/03
نویسنده
چکیده
The 25 nm physical gate length transistor for microprocessor units is scheduled for production on the International Technology Roadmap for Semiconductors (ITRS) roadmap for 2007 [1]. Presently, this pushes device engineers to consider developing such transistors because there is a lag of several years between device design and process integration. This paper reports on the methods and design of a silicon bulk-PMOS that operates with a 0.8 V supply voltage. This design is appealing because it offers benefits in scalability and reliability of silicon technology. Results are given from simulation in Tsuprem4 and Medici. For a 100 nm physical gate PMOS, VTlin = -159.9 mV. For a 25 nm physical gate PMOS, |Ion| (VGS=0V,VDS=-VDD) = 302uA/um, |Ioff| (VGS=0V, VDS=-VDD) = 230 nA/um, VTlin = 85 mV, VTsat = -10 mV, VTlin roll-off from long channel = 75 mV, DIBL (|VTlin| – |VTsat|) = 75 mV, and subthreshold slope = 83.16 mV/dec.
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